Output Network.


Some thought and a few simulations were needed to find a better choice of output network, and some of the more interesting results are shown next. They are all, in effect, small-signal simulations which ignore nonlinearity, the only aim being to determine stability margins.
The conditions for stability can be different for a nonlinear system, but the only serious nonlinearity in this application is at clipping, and this is checked here by looking at what happens when the cascode stage starts to clip and therefore its output impedance falls, but again this is a linear 'small-signal' approximation so not entirely correct. Analysis of nonlinear systems is notoriously difficult, and simulations not entirely dependable, so testing of a real amplifier when clipping into various loads is still a good idea.

The high feedback used is not itself a problem, instability normally only occurs at the loop unity gain frequency, not at frequencies where the loop gain is high. One problem is that the unity gain frequency is not fixed, partly because the series resonance with the output inductor and a capacitor load can reduce gain to unity over a range of frequencies for different capacitances, but also it can change over a wide range near clipping. Some designs can have short bursts of high frequency oscillation when coming out of clipping, and even if this has no audible effect there could be interference with other equipment, so it needs to be avoided.

The problem then is to prevent the excess phase lag round the feedback loop approaching too close to 180 deg at the same frequency where the gain round the loop is unity, and achieving this for any reasonable load and any level of clipping. There are inevitably different opinions about what loads should be regarded as 'reasonable'.

The next diagrams are phase shift and gain round the feedback loop with a 4uF load, and without the 100n + 1R across the load. The first has a 7R5 damping resistor across the inductor.

( The apparent discontinuity in the top phase plot happens because AIM-Spice only plots phase from -180 to +180 degrees, and anything more negative than minus 180 becomes a positive phase, so the sudden jump is of no real significance. A 1V input to the feedback loop was used, so the voltage in the lower plot is equal to the loop gain.)

Although the phase exceeds 180 deg. from 40kHz to above 100kHz the gain only falls to unity slightly above this range, so it may just avoid instability, but the safety margin is far too small. To improve the stability margin to a more acceptable level the damping resistor can be reduced. In the next diagram it is 2R2.

This is better, the gain falls only to 2, at a frequency around 120kHz, with about 90 deg phase shift, and is about 10 when the phase shift reaches 180 deg.

The phase lag still exceeds 180 deg over a range of frequencies. Where this may become a problem is near clipping where the gain can reduce to unity in the frequency range where phase exceeded 180 deg. Fortunately with the method of high frequency compensation used the phase shift also reduces near clipping, and to simulate this effect we can reduce the impedance at the output of the cascode stage, which will be the initial effect as we approach clipping (which is why we want the driver stage to clip first before the output stage). Reducing this impedance from its normal value of 200k down to 3k, again with the 4uF load, gives the following result:

This impedance reduction is sufficient to reduce loop gain to unity around 120kHz, but the maximum phase shift falls to 120 deg around 90kHz. At the 120kHz unity gain frequency we have a 90 deg phase margin, so clipping is no problem in this case.

The problem of high capacitance loads may be solved, but reducing the damping resistor can make things worse at higher frequencies where the instability found in the original MJR-7 with loads around 2nF may still remain. This was caused by the 2nF having a series resonance with the output inductor close to the unity gain frequency. Adding 100nF across the load prevents the total capacitance being as low as 2nF and so avoids this problem but replaces it with another. Adding an inductive load there will then be a resonance with the 100n, and the result could still be capacitive at the originally problematic frequency. The next diagram is with the 100n added together with a load of 0.05uH

This shows large gain and phase effects above 2MHz, and in combination with other phase shifts, e.g. from the input stage, which has been ignored here, there could still be a stability problem. It may be highly unlikely that any speaker plus cable would have a pure inductance of 0.05uH at 2.5MHz, but it is easy to prevent the problem. The solution is to add a small resistor in series with the 100n to damp any resonances. 1R was found to give adequate damping, 0R5 or smaller values still gave a noticeable notch in the phase response. The result with 1R added is shown next.

The final version, as shown in the circuit diagram, has phase shift round the feedback loop which only reaches 180 deg for capacitive loads 2uF or more. The next diagram shows the result with a 2uF load added.

Other simulations were tried, and here is a summary of the more useful results:
With inductor 0.8uH to match the calculated value all stability margins were improved, so if this is the correct value this is no problem.
With source impedance increased from the 600R used for the above results there was some reduction in stability margin, but not enough to be a problem.
With mosfet capacitances doubled to simulate the dual die types or parallel pairs there was no serious problem, but reducing total quiescent current below 100mA should then be avoided.
The small negative resistance output impedance at very low frequencies was investigated and found to be a maximum of 0.09 ohms around 6Hz. Increasing the 10uF in the feedback network increases this value, so is not a good idea. Reducing the 10uF increases the effect of the output capacitor a little.


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